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| author | Frank Chang | 2022-09-09 15:42:09 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-09-27 03:23:57 +0200 |
| commit | 9d5a84db91f12bd843206a57e0cde01e6a9d488d (patch) | |
| tree | d86d750ae4e0c10ce7e16c5fa97fa32b3598d680 | |
| parent | target/riscv: debug: Determine the trigger type from tdata1.type (diff) | |
| download | qemu-9d5a84db91f12bd843206a57e0cde01e6a9d488d.tar.gz qemu-9d5a84db91f12bd843206a57e0cde01e6a9d488d.tar.xz qemu-9d5a84db91f12bd843206a57e0cde01e6a9d488d.zip | |
target/riscv: debug: Introduce build_tdata1() to build tdata1 register content
Introduce build_tdata1() to build tdata1 register content, which can be
shared among all types of triggers.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
[bmeng: moved RV{32,64}_DATA_MASK definition to this patch]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220909134215.1843865-3-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/debug.c | 15 | ||||
| -rw-r--r-- | target/riscv/debug.h | 2 |
2 files changed, 12 insertions, 5 deletions
diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 9dd468753a..45aae87ec3 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -95,18 +95,23 @@ static inline target_ulong get_trigger_type(CPURISCVState *env, return extract_trigger_type(env, tdata1); } -static inline target_ulong trigger_type(CPURISCVState *env, - trigger_type_t type) +static inline target_ulong build_tdata1(CPURISCVState *env, + trigger_type_t type, + bool dmode, target_ulong data) { target_ulong tdata1; switch (riscv_cpu_mxl(env)) { case MXL_RV32: - tdata1 = RV32_TYPE(type); + tdata1 = RV32_TYPE(type) | + (dmode ? RV32_DMODE : 0) | + (data & RV32_DATA_MASK); break; case MXL_RV64: case MXL_RV128: - tdata1 = RV64_TYPE(type); + tdata1 = RV64_TYPE(type) | + (dmode ? RV64_DMODE : 0) | + (data & RV64_DATA_MASK); break; default: g_assert_not_reached(); @@ -495,7 +500,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) void riscv_trigger_init(CPURISCVState *env) { - target_ulong tdata1 = trigger_type(env, TRIGGER_TYPE_AD_MATCH); + target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0); int i; /* init to type 2 triggers */ diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 72e4edcd8c..c422553c27 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -56,9 +56,11 @@ typedef struct { #define RV32_TYPE(t) ((uint32_t)(t) << 28) #define RV32_TYPE_MASK (0xf << 28) #define RV32_DMODE BIT(27) +#define RV32_DATA_MASK 0x7ffffff #define RV64_TYPE(t) ((uint64_t)(t) << 60) #define RV64_TYPE_MASK (0xfULL << 60) #define RV64_DMODE BIT_ULL(59) +#define RV64_DATA_MASK 0x7ffffffffffffff /* mcontrol field masks */ |