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| author | Alex Williamson | 2018-12-12 20:40:09 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin | 2018-12-19 22:48:16 +0100 |
| commit | a09d2038cc5f8e45e2126461e5fb1eb9f4874be3 (patch) | |
| tree | 0b0725d3776c0fa46803ea5ba9c5c6018afb9fe6 | |
| parent | vfio/pci: Remove PCIe Link Status emulation (diff) | |
| download | qemu-a09d2038cc5f8e45e2126461e5fb1eb9f4874be3.tar.gz qemu-a09d2038cc5f8e45e2126461e5fb1eb9f4874be3.tar.xz qemu-a09d2038cc5f8e45e2126461e5fb1eb9f4874be3.zip | |
pcie: Fast PCIe root ports for new machines
Change the default speed and width for new machine types to the
fastest and widest currently supported. This should be compatible to
the PCIe 4.0 spec. Pre-QEMU-4.0 machine types remain at 2.5GT/s, x1
width.
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| -rw-r--r-- | hw/pci-bridge/gen_pcie_root_port.c | 4 | ||||
| -rw-r--r-- | include/hw/compat.h | 10 |
2 files changed, 11 insertions, 3 deletions
diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c index ca5418a89d..9766edb445 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -125,9 +125,9 @@ static Property gen_rp_props[] = { DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, res_reserve.mem_pref_64, -1), DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot, - speed, PCIE_LINK_SPEED_2_5), + speed, PCIE_LINK_SPEED_16), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, - width, PCIE_LINK_WIDTH_1), + width, PCIE_LINK_WIDTH_32), DEFINE_PROP_END_OF_LIST() }; diff --git a/include/hw/compat.h b/include/hw/compat.h index 70958328fe..3ca85b037c 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -2,7 +2,15 @@ #define HW_COMPAT_H #define HW_COMPAT_3_1 \ - /* empty */ + {\ + .driver = "pcie-root-port",\ + .property = "x-speed",\ + .value = "2_5",\ + },{\ + .driver = "pcie-root-port",\ + .property = "x-width",\ + .value = "1",\ + }, #define HW_COMPAT_3_0 \ /* empty */ |