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| author | Peter Maydell | 2019-07-09 12:49:26 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-07-09 12:49:26 +0200 |
| commit | a538626aff7c8934ec47bc6ed41cac5bd1b7723c (patch) | |
| tree | fa5d877c4858eeded149428d8ba426f8af5fd12a | |
| parent | Merge remote-tracking branch 'remotes/stefanberger/tags/pull-tpm-2019-07-08-1... (diff) | |
| parent | tcg: Fix expansion of INDEX_op_not_vec (diff) | |
| download | qemu-a538626aff7c8934ec47bc6ed41cac5bd1b7723c.tar.gz qemu-a538626aff7c8934ec47bc6ed41cac5bd1b7723c.tar.xz qemu-a538626aff7c8934ec47bc6ed41cac5bd1b7723c.zip | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190709' into staging
Minor gvec fix for as-yet uncommitted altivec host.
Build fix for riscv host.
# gpg: Signature made Tue 09 Jul 2019 07:27:34 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-20190709:
tcg: Fix expansion of INDEX_op_not_vec
tcg/riscv: Fix RISC-VH host build failure
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | tcg/riscv/tcg-target.inc.c | 4 | ||||
| -rw-r--r-- | tcg/tcg-op-vec.c | 6 |
2 files changed, 8 insertions, 2 deletions
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 1f0ae64aae..3e76bf5738 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -980,8 +980,8 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index c8fdc24f56..6714991bf4 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -90,6 +90,9 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, case INDEX_op_bitsel_vec: /* These opcodes are mandatory and should not be listed. */ g_assert_not_reached(); + case INDEX_op_not_vec: + /* These opcodes have generic expansions using the above. */ + g_assert_not_reached(); default: break; } @@ -438,11 +441,14 @@ static bool do_op2(unsigned vece, TCGv_vec r, TCGv_vec a, TCGOpcode opc) void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a) { + const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); + if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) { TCGv_vec t = tcg_const_ones_vec_matching(r); tcg_gen_xor_vec(0, r, a, t); tcg_temp_free_vec(t); } + tcg_swap_vecop_list(hold_list); } void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a) |