diff options
| author | Alexander Graf | 2014-06-04 02:01:10 +0200 |
|---|---|---|
| committer | Alexander Graf | 2014-06-16 13:24:41 +0200 |
| commit | ada82b537e6fa947666a7cda1530529769a9324c (patch) | |
| tree | f06fc3459ac3265ccf63fbef13b1358f10b655f4 | |
| parent | PPC: e500: Fix TLB lookup for 32bit CPUs (diff) | |
| download | qemu-ada82b537e6fa947666a7cda1530529769a9324c.tar.gz qemu-ada82b537e6fa947666a7cda1530529769a9324c.tar.xz qemu-ada82b537e6fa947666a7cda1530529769a9324c.zip | |
PPC: SPE: Fix high-bits bitmask
The SPE emulation code wants to access the highest 32bits of a 64bit register
and uses the andi TCG instruction for that. Unfortunately it masked with the
wrong mask. Fix the mask to actually cover the upper 32 bits.
This fixes simple multiplication tests with SPE guests for me.
Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | target-ppc/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 715bc74ea8..5cc5afd7bf 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -8718,7 +8718,7 @@ static inline void gen_evmergehi(DisasContext *ctx) TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); - tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); + tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL); tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); tcg_temp_free(t0); tcg_temp_free(t1); @@ -8888,7 +8888,7 @@ static inline void gen_evmergehilo(DisasContext *ctx) TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); - tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); + tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL); tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); tcg_temp_free(t0); tcg_temp_free(t1); |