summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorPeter Maydell2018-02-15 19:29:37 +0100
committerPeter Maydell2018-02-15 19:29:49 +0100
commitae7c5c855b71f2de23dbad3b97bbe1c0375d6fd3 (patch)
tree474d9749c0c2ac3f00373be10c77212e54bc29d4
parenthw/intc/armv7m_nvic: Implement M profile cache maintenance ops (diff)
downloadqemu-ae7c5c855b71f2de23dbad3b97bbe1c0375d6fd3.tar.gz
qemu-ae7c5c855b71f2de23dbad3b97bbe1c0375d6fd3.tar.xz
qemu-ae7c5c855b71f2de23dbad3b97bbe1c0375d6fd3.zip
hw/intc/armv7m_nvic: Implement v8M CPPWR register
The Coprocessor Power Control Register (CPPWR) is new in v8M. It allows software to control whether coprocessors are allowed to power down and lose their state. QEMU doesn't have any notion of power control, so we choose the IMPDEF option of making the whole register RAZ/WI (indicating that no coprocessors can ever power down and lose state). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180209165810.6668-5-peter.maydell@linaro.org
-rw-r--r--hw/intc/armv7m_nvic.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 74b25ce92c..eb49fd77c7 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -776,6 +776,14 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
switch (offset) {
case 4: /* Interrupt Control Type. */
return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
+ case 0xc: /* CPPWR */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
+ goto bad_offset;
+ }
+ /* We make the IMPDEF choice that nothing can ever go into a
+ * non-retentive power state, which allows us to RAZ/WI this.
+ */
+ return 0;
case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
{
int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
@@ -1175,6 +1183,12 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
ARMCPU *cpu = s->cpu;
switch (offset) {
+ case 0xc: /* CPPWR */
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
+ goto bad_offset;
+ }
+ /* Make the IMPDEF choice to RAZ/WI this. */
+ break;
case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
{
int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;