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| author | Andrew Jeffery | 2021-03-09 12:01:28 +0100 |
|---|---|---|
| committer | Cédric Le Goater | 2021-03-09 12:01:28 +0100 |
| commit | b151de69f6478a05b27f4be2eb4a906f7b5b8cfa (patch) | |
| tree | 66db8b017d00023475e6f87532acabadb57ead30 | |
| parent | hw/arm: ast2600: Force a multiple of 32 of IRQs for the GIC (diff) | |
| download | qemu-b151de69f6478a05b27f4be2eb4a906f7b5b8cfa.tar.gz qemu-b151de69f6478a05b27f4be2eb4a906f7b5b8cfa.tar.xz qemu-b151de69f6478a05b27f4be2eb4a906f7b5b8cfa.zip | |
hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet
The datasheet says we have 197 IRQs allocated, and we need more than 128
to describe IRQs from LPC devices. Raise the value now to allow
modelling of the LPC devices.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210302014317.915120-3-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| -rw-r--r-- | hw/arm/aspeed_ast2600.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 3d9e78fcc6..1dc56ce478 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -65,7 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { #define ASPEED_A7MPCORE_ADDR 0x40460000 -#define AST2600_MAX_IRQ 128 +#define AST2600_MAX_IRQ 197 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ static const int aspeed_soc_ast2600_irqmap[] = { |