diff options
| author | Peter Maydell | 2017-01-20 12:15:08 +0100 |
|---|---|---|
| committer | Peter Maydell | 2017-01-20 12:15:08 +0100 |
| commit | b53db42bc0140a32e5196125b216a82d08992a7d (patch) | |
| tree | 955ba2ea861f7add661cfb67b00795c13db51736 | |
| parent | hw/arm/virt-acpi - reserve ECAM space as PNP0C02 device (diff) | |
| download | qemu-b53db42bc0140a32e5196125b216a82d08992a7d.tar.gz qemu-b53db42bc0140a32e5196125b216a82d08992a7d.tar.xz qemu-b53db42bc0140a32e5196125b216a82d08992a7d.zip | |
hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ
Augment the GICv3's QOM device interface by adding two
new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to
each CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 1483977924-14522-2-git-send-email-peter.maydell@linaro.org
| -rw-r--r-- | hw/intc/arm_gicv3_common.c | 6 | ||||
| -rw-r--r-- | include/hw/intc/arm_gicv3_common.h | 2 |
2 files changed, 8 insertions, 0 deletions
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 0aa9b9ca66..0ee67a40b5 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -126,6 +126,12 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, for (i = 0; i < s->num_cpu; i++) { sysbus_init_irq(sbd, &s->cpu[i].parent_fiq); } + for (i = 0; i < s->num_cpu; i++) { + sysbus_init_irq(sbd, &s->cpu[i].parent_virq); + } + for (i = 0; i < s->num_cpu; i++) { + sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq); + } memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s, "gicv3_dist", 0x10000); diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index 341a3118f0..beb2c7763e 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -145,6 +145,8 @@ struct GICv3CPUState { CPUState *cpu; qemu_irq parent_irq; qemu_irq parent_fiq; + qemu_irq parent_virq; + qemu_irq parent_vfiq; /* Redistributor */ uint32_t level; /* Current IRQ level */ |