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| author | Isaku Yamahata | 2010-11-19 12:28:45 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin | 2010-11-22 09:00:06 +0100 |
| commit | bba5ed772a562fefdb218df8d821c3b537ce5759 (patch) | |
| tree | 56f87300e53e57a4544317b26e739345eb4776d1 | |
| parent | pci: fix bridge control bit wmask (diff) | |
| download | qemu-bba5ed772a562fefdb218df8d821c3b537ce5759.tar.gz qemu-bba5ed772a562fefdb218df8d821c3b537ce5759.tar.xz qemu-bba5ed772a562fefdb218df8d821c3b537ce5759.zip | |
pcie/port: fix bridge control register wmask
pci generic layer initialized wmask for bridge control register
according to pci spec. pcie deviates slightly from it,
so initialize it properly.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| -rw-r--r-- | hw/pcie_port.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/hw/pcie_port.c b/hw/pcie_port.c index 117de6186e..340dcdb3c4 100644 --- a/hw/pcie_port.c +++ b/hw/pcie_port.c @@ -27,6 +27,14 @@ void pcie_port_init_reg(PCIDevice *d) pci_set_word(d->config + PCI_STATUS, 0); pci_set_word(d->config + PCI_SEC_STATUS, 0); + /* Unlike conventional pci bridge, some bits are hardwared to 0. */ + pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, + PCI_BRIDGE_CTL_PARITY | + PCI_BRIDGE_CTL_ISA | + PCI_BRIDGE_CTL_VGA | + PCI_BRIDGE_CTL_SERR | + PCI_BRIDGE_CTL_BUS_RESET); + /* 7.5.3.5 Prefetchable Memory Base Limit * The Prefetchable Memory Base and Prefetchable Memory Limit registers * must indicate that 64-bit addresses are supported, as defined in |