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| author | Hervé Poussineau | 2015-06-03 22:45:49 +0200 |
|---|---|---|
| committer | Leon Alrae | 2015-06-11 11:13:30 +0200 |
| commit | bd8f1ebce430eb6c1dd92e34baf7bc35aa600464 (patch) | |
| tree | e320cabafba3b778a0cc0b977450a2f1b0024df5 | |
| parent | net/dp8393x: correctly reset in_use field (diff) | |
| download | qemu-bd8f1ebce430eb6c1dd92e34baf7bc35aa600464.tar.gz qemu-bd8f1ebce430eb6c1dd92e34baf7bc35aa600464.tar.xz qemu-bd8f1ebce430eb6c1dd92e34baf7bc35aa600464.zip | |
net/dp8393x: fix hardware reset
Documentation is not clear of what happens when doing a hardware reset,
but firmware expect all registers to be zero unless specified otherwise.
This fixes reboot on MIPS Magnum.
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| -rw-r--r-- | hw/net/dp8393x.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index ff633f76a0..cd889bce86 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -786,6 +786,7 @@ static void dp8393x_reset(DeviceState *dev) dp8393xState *s = DP8393X(dev); timer_del(s->watchdog); + memset(s->regs, 0, sizeof(s->regs)); s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT); |