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| author | Alistair Francis | 2021-10-22 08:01:30 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-10-28 06:39:23 +0200 |
| commit | bf357e1d72cd8b7b590518dacdf4b65beb2c61e2 (patch) | |
| tree | de9048d963d3ad62e876083564fa2189b1079e6d | |
| parent | hw/riscv: virt: Don't use a macro for the PLIC configuration (diff) | |
| download | qemu-bf357e1d72cd8b7b590518dacdf4b65beb2c61e2.tar.gz qemu-bf357e1d72cd8b7b590518dacdf4b65beb2c61e2.tar.xz qemu-bf357e1d72cd8b7b590518dacdf4b65beb2c61e2.zip | |
hw/riscv: boot: Add a PLIC config string function
Add a generic function that can create the PLIC strings.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211022060133.3045020-2-alistair.francis@opensource.wdc.com
| -rw-r--r-- | hw/riscv/boot.c | 25 | ||||
| -rw-r--r-- | include/hw/riscv/boot.h | 2 |
2 files changed, 27 insertions, 0 deletions
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index d1ffc7b56c..519fa455a1 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -38,6 +38,31 @@ bool riscv_is_32bit(RISCVHartArrayState *harts) return harts->harts[0].env.misa_mxl_max == MXL_RV32; } +/* + * Return the per-socket PLIC hart topology configuration string + * (caller must free with g_free()) + */ +char *riscv_plic_hart_config_string(int hart_count) +{ + g_autofree const char **vals = g_new(const char *, hart_count + 1); + int i; + + for (i = 0; i < hart_count; i++) { + CPUState *cs = qemu_get_cpu(i); + CPURISCVState *env = &RISCV_CPU(cs)->env; + + if (riscv_has_ext(env, RVS)) { + vals[i] = "MS"; + } else { + vals[i] = "M"; + } + } + vals[i] = NULL; + + /* g_strjoinv() obliges us to cast away const here */ + return g_strjoinv(",", (char **)vals); +} + target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, target_ulong firmware_end_addr) { if (riscv_is_32bit(harts)) { diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 0e89400b09..baff11dd8a 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -31,6 +31,8 @@ bool riscv_is_32bit(RISCVHartArrayState *harts); +char *riscv_plic_hart_config_string(int hart_count); + target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, target_ulong firmware_end_addr); target_ulong riscv_find_and_load_firmware(MachineState *machine, |