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| author | Aurelien Jarno | 2012-09-16 13:12:20 +0200 |
|---|---|---|
| committer | Aurelien Jarno | 2012-09-21 19:53:16 +0200 |
| commit | c53b36d210a55c67eca3ae89ebfdf665c0f2c3e2 (patch) | |
| tree | 99d8eacdc4ebe6a83b9768520a3d95856e5c82a3 | |
| parent | target-sh4: optimize xtrct (diff) | |
| download | qemu-c53b36d210a55c67eca3ae89ebfdf665c0f2c3e2.tar.gz qemu-c53b36d210a55c67eca3ae89ebfdf665c0f2c3e2.tar.xz qemu-c53b36d210a55c67eca3ae89ebfdf665c0f2c3e2.zip | |
target-sh4: optimize swap.w
It's possible swap the two 16-bit words of a 32-bit register using a
rotation. If the TCG target doesn't implement rotation, the replacement
code is similar to the previously implemented code.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | target-sh4/translate.c | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 92c5a1fb6d..9ecbe471e6 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -732,17 +732,7 @@ static void _decode_opc(DisasContext * ctx) } return; case 0x6009: /* swap.w Rm,Rn */ - { - TCGv high, low; - high = tcg_temp_new(); - tcg_gen_shli_i32(high, REG(B7_4), 16); - low = tcg_temp_new(); - tcg_gen_shri_i32(low, REG(B7_4), 16); - tcg_gen_ext16u_i32(low, low); - tcg_gen_or_i32(REG(B11_8), high, low); - tcg_temp_free(low); - tcg_temp_free(high); - } + tcg_gen_rotli_i32(REG(B11_8), REG(B7_4), 16); return; case 0x200d: /* xtrct Rm,Rn */ { |