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| author | Richard Sandiford | 2013-01-20 20:30:54 +0100 |
|---|---|---|
| committer | Aurelien Jarno | 2013-01-31 23:40:52 +0100 |
| commit | c728154bbbc1a86465a0fd6bfc839bc9710ac374 (patch) | |
| tree | d2011cf8167adb8939c5d464958cbac9fe46ec4e | |
| parent | target-mips: Fix signedness of loads in MIPS16 RESTOREs (diff) | |
| download | qemu-c728154bbbc1a86465a0fd6bfc839bc9710ac374.tar.gz qemu-c728154bbbc1a86465a0fd6bfc839bc9710ac374.tar.xz qemu-c728154bbbc1a86465a0fd6bfc839bc9710ac374.zip | |
target-mips: Sign-extend the result of LWR
Sign-extend the result of LWR, as is already done for LWL. This is necessary
in the case where LWR loads the full word (i.e. the address is actually
aligned). In the other cases, it is implementation defined whether the
upper 32 bits of the result are unchanged or a copy of bit 31. The latter
seems easier to implement.
Previously the code used:
(oldval & (0xfffffffe << (31 - bitshift))) | (newval >> bitshift)
which zeroed the upper bits of the register, losing any previous sign
extension in the unaligned cases.
Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | target-mips/translate.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 8520d28519..e58d916b04 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1745,6 +1745,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); tcg_temp_free(t1); + tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, rt); opn = "lwr"; break; |