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| author | Peter Maydell | 2016-07-29 14:05:55 +0200 |
|---|---|---|
| committer | Peter Maydell | 2016-07-29 14:05:55 +0200 |
| commit | c7e9aafe5c2fc82858a3026862ac05c33d363ffb (patch) | |
| tree | 9127089af696376063b96bfa0e6d7260632daa60 | |
| parent | Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160729' into... (diff) | |
| parent | target-mips: fix EntryHi.EHINV being cleared on TLB exception (diff) | |
| download | qemu-c7e9aafe5c2fc82858a3026862ac05c33d363ffb.tar.gz qemu-c7e9aafe5c2fc82858a3026862ac05c33d363ffb.tar.xz qemu-c7e9aafe5c2fc82858a3026862ac05c33d363ffb.zip | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160729' into staging
MIPS patches 2016-07-29
Changes:
* bug fixes
# gpg: Signature made Fri 29 Jul 2016 09:44:13 BST
# gpg: using RSA key 0x52118E3C0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B
* remotes/lalrae/tags/mips-20160729:
target-mips: fix EntryHi.EHINV being cleared on TLB exception
hw/mips_malta: Fix YAMON API print routine
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/mips/mips_malta.c | 2 | ||||
| -rw-r--r-- | target-mips/helper.c | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 34d41ef44a..e90857ee0b 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -727,7 +727,7 @@ static void write_bootloader(uint8_t *base, int64_t run_addr, stl_p(p++, 0x00000000); /* nop */ stl_p(p++, 0x0ff0021c); /* jal 870 */ stl_p(p++, 0x00000000); /* nop */ - stl_p(p++, 0x08000205); /* j 814 */ + stl_p(p++, 0x1000fff9); /* b 814 */ stl_p(p++, 0x00000000); /* nop */ stl_p(p++, 0x01a00009); /* jalr t5 */ stl_p(p++, 0x01602021); /* move a0,t3 */ diff --git a/target-mips/helper.c b/target-mips/helper.c index 9fbca26d41..c864b15b97 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -396,6 +396,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, env->CP0_Context = (env->CP0_Context & ~0x007fffff) | ((address >> 9) & 0x007ffff0); env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) | + (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) | (address & (TARGET_PAGE_MASK << 1)); #if defined(TARGET_MIPS64) env->CP0_EntryHi &= env->SEGMask; |