diff options
| author | Rémi Denis-Courmont | 2021-01-12 11:44:53 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-01-19 15:38:51 +0100 |
| commit | cc974d5cd84ea60a3dad59752aea712f3d47f8ce (patch) | |
| tree | 1b3ce0fe25a5e1627217120420cb6cd2970fe9a5 | |
| parent | target/arm: Use object_property_add_bool for "sve" property (diff) | |
| download | qemu-cc974d5cd84ea60a3dad59752aea712f3d47f8ce.tar.gz qemu-cc974d5cd84ea60a3dad59752aea712f3d47f8ce.tar.xz qemu-cc974d5cd84ea60a3dad59752aea712f3d47f8ce.zip | |
target/arm: remove redundant tests
In this context, the HCR value is the effective value, and thus is
zero in secure mode. The tests for HCR.{F,I}MO are sufficient.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-1-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/cpu.c | 8 | ||||
| -rw-r--r-- | target/arm/helper.c | 10 |
2 files changed, 8 insertions, 10 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index be18df5464..4ae22b2086 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -451,14 +451,14 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, break; case EXCP_VFIQ: - if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { - /* VFIQs are only taken when hypervized and non-secure. */ + if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { + /* VFIQs are only taken when hypervized. */ return false; } return !(env->daif & PSTATE_F); case EXCP_VIRQ: - if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { - /* VIRQs are only taken when hypervized and non-secure. */ + if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { + /* VIRQs are only taken when hypervized. */ return false; } return !(env->daif & PSTATE_I); diff --git a/target/arm/helper.c b/target/arm/helper.c index c5377e7ecb..b2ea93c472 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2084,13 +2084,11 @@ static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) { CPUState *cs = env_cpu(env); - uint64_t hcr_el2 = arm_hcr_el2_eff(env); + bool el1 = arm_current_el(env) == 1; + uint64_t hcr_el2 = el1 ? arm_hcr_el2_eff(env) : 0; uint64_t ret = 0; - bool allow_virt = (arm_current_el(env) == 1 && - (!arm_is_secure_below_el3(env) || - (env->cp15.scr_el3 & SCR_EEL2))); - if (allow_virt && (hcr_el2 & HCR_IMO)) { + if (hcr_el2 & HCR_IMO) { if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { ret |= CPSR_I; } @@ -2100,7 +2098,7 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) } } - if (allow_virt && (hcr_el2 & HCR_FMO)) { + if (hcr_el2 & HCR_FMO) { if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { ret |= CPSR_F; } |