diff options
| author | Philippe Mathieu-Daudé | 2021-10-14 17:45:29 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-10-18 00:41:36 +0200 |
| commit | cfddceba7f9f56a5564015962154dccd242f5c8b (patch) | |
| tree | 054ef82fba3122ad67fc49b8200e430c59d62ddb | |
| parent | target/mips: Fix DEXTRV_S.H DSP opcode (diff) | |
| download | qemu-cfddceba7f9f56a5564015962154dccd242f5c8b.tar.gz qemu-cfddceba7f9f56a5564015962154dccd242f5c8b.tar.xz qemu-cfddceba7f9f56a5564015962154dccd242f5c8b.zip | |
target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()
Since gen_mipsdsp_accinsn() got added in commit b53371ed5d4
("target-mips: Add ASE DSP accumulator instructions"), the
'v2_t' TCG temporary has never been used. Remove it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211014224551.2204949-1-f4bug@amsat.org>
| -rw-r--r-- | target/mips/tcg/translate.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 519b00121f..47db35d7dd 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -13616,7 +13616,6 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, TCGv t0; TCGv t1; TCGv v1_t; - TCGv v2_t; int16_t imm; if ((ret == 0) && (check_ret == 1)) { @@ -13627,10 +13626,8 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, t0 = tcg_temp_new(); t1 = tcg_temp_new(); v1_t = tcg_temp_new(); - v2_t = tcg_temp_new(); gen_load_gpr(v1_t, v1); - gen_load_gpr(v2_t, v2); switch (op1) { case OPC_EXTR_W_DSP: @@ -13830,7 +13827,6 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, tcg_temp_free(t0); tcg_temp_free(t1); tcg_temp_free(v1_t); - tcg_temp_free(v2_t); } /* End MIPSDSP functions. */ |