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author | Richard Henderson | 2022-03-01 22:59:46 +0100 |
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committer | Peter Maydell | 2022-03-02 20:27:36 +0100 |
commit | d06449f2eb555896057ee047b3009a3616d52028 (patch) | |
tree | f1291ad63a9d0fa9a4a121ff3f44aeb72ee33881 | |
parent | target/arm: Pass outputsize down to check_s2_mmu_setup (diff) | |
download | qemu-d06449f2eb555896057ee047b3009a3616d52028.tar.gz qemu-d06449f2eb555896057ee047b3009a3616d52028.tar.xz qemu-d06449f2eb555896057ee047b3009a3616d52028.zip |
target/arm: Use MAKE_64BIT_MASK to compute indexmask
The macro is a bit more readable than the inlined computation.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | target/arm/helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 431b0c1405..675aec4bf3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11518,8 +11518,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, level = startlevel; } - indexmask_grainsize = (1ULL << (stride + 3)) - 1; - indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; + indexmask_grainsize = MAKE_64BIT_MASK(0, stride + 3); + indexmask = MAKE_64BIT_MASK(0, inputsize - (stride * (4 - level))); /* Now we can extract the actual base address from the TTBR */ descaddr = extract64(ttbr, 0, 48); |