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| author | Leon Alrae | 2014-06-27 09:49:07 +0200 |
|---|---|---|
| committer | Leon Alrae | 2014-10-14 14:28:52 +0200 |
| commit | ddc584bdb5375f260e7dcec3831d1bb32f665d25 (patch) | |
| tree | dcaf1319050249cc46a5ff414aa705d42452a181 | |
| parent | target-mips: add new Floating Point Comparison instructions (diff) | |
| download | qemu-ddc584bdb5375f260e7dcec3831d1bb32f665d25.tar.gz qemu-ddc584bdb5375f260e7dcec3831d1bb32f665d25.tar.xz qemu-ddc584bdb5375f260e7dcec3831d1bb32f665d25.zip | |
target-mips: do not allow Status.FR=0 mode in 64-bit FPU
Status.FR bit must be ignored on write and read as 1 when an implementation of
Release 6 of the Architecture in which a 64-bit floating point unit is
implemented.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
| -rw-r--r-- | target-mips/translate.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 6f57171912..80887812ca 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -17951,6 +17951,12 @@ void cpu_state_reset(CPUMIPSState *env) } } #endif + if ((env->insn_flags & ISA_MIPS32R6) && + (env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ + env->CP0_Status |= (1 << CP0St_FR); + } + compute_hflags(env); cs->exception_index = EXCP_NONE; } |