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| author | Stafford Horne | 2018-07-01 10:02:54 +0200 |
|---|---|---|
| committer | Stafford Horne | 2018-07-03 15:40:33 +0200 |
| commit | dfc84745bbaa0fea2abc8575dd349f6e4bb7edc7 (patch) | |
| tree | 2bff594c72320e543d793c20890dee4590047221 | |
| parent | target/openrisc: Fix delay slot exception flag to match spec (diff) | |
| download | qemu-dfc84745bbaa0fea2abc8575dd349f6e4bb7edc7.tar.gz qemu-dfc84745bbaa0fea2abc8575dd349f6e4bb7edc7.tar.xz qemu-dfc84745bbaa0fea2abc8575dd349f6e4bb7edc7.zip | |
target/openrisc: Fix writes to interrupt mask register
The interrupt controller mask register (PICMR) allows writing any value
to any of the 32 interrupt mask bits. Writing a 0 masks the interrupt
writing a 1 unmasks (enables) the the interrupt.
For some reason the old code was or'ing the write values to the PICMR
meaning it was not possible to ever mask a interrupt once it was
enabled.
I have tested this by running linux 4.18 and my regular checks, I don't
see any issues.
Reported-by: Davidson Francis <davidsondfgl@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
| -rw-r--r-- | target/openrisc/sys_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 541615bfb3..b66a45c1e0 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -142,7 +142,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) } break; case TO_SPR(9, 0): /* PICMR */ - env->picmr |= rb; + env->picmr = rb; break; case TO_SPR(9, 2): /* PICSR */ env->picsr &= ~rb; |