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| author | Eugene Minibaev | 2018-04-06 15:41:52 +0200 |
|---|---|---|
| committer | Paolo Bonzini | 2018-04-09 16:36:40 +0200 |
| commit | e0014d4b3a955cfd8d517674703bfa87f340290a (patch) | |
| tree | 9740a3f07e2ddcbb1bf3e27846a463ea160fbf29 | |
| parent | maint: Add .mailmap entries for patches claiming list authorship (diff) | |
| download | qemu-e0014d4b3a955cfd8d517674703bfa87f340290a.tar.gz qemu-e0014d4b3a955cfd8d517674703bfa87f340290a.tar.xz qemu-e0014d4b3a955cfd8d517674703bfa87f340290a.zip | |
Add missing bit for SSE instr in VEX decoding
The 2-byte VEX prefix imples a leading 0Fh opcode byte.
Signed-off-by: Eugene Minibaev <mail@kitsu.me>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/translate.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/i386/translate.c b/target/i386/translate.c index 3b7ce9232e..c9ed8dc709 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -4563,9 +4563,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) #endif rex_r = (~vex2 >> 4) & 8; if (b == 0xc5) { + /* 2-byte VEX prefix: RVVVVlpp, implied 0f leading opcode byte */ vex3 = vex2; - b = x86_ldub_code(env, s); + b = x86_ldub_code(env, s) | 0x100; } else { + /* 3-byte VEX prefix: RXBmmmmm wVVVVlpp */ #ifdef TARGET_X86_64 s->rex_x = (~vex2 >> 3) & 8; s->rex_b = (~vex2 >> 2) & 8; |