diff options
| author | Stephen Long | 2020-08-13 18:18:18 +0200 |
|---|---|---|
| committer | Richard Henderson | 2020-09-03 22:13:58 +0200 |
| commit | e7e8f33fb603c3bfa0479d7d924f2ad676a84317 (patch) | |
| tree | 150238a865a0d7bdaf1297ce540c17e4417f9f01 | |
| parent | cputlb: Make store_helper less fragile to compiler optimizations (diff) | |
| download | qemu-e7e8f33fb603c3bfa0479d7d924f2ad676a84317.tar.gz qemu-e7e8f33fb603c3bfa0479d7d924f2ad676a84317.tar.xz qemu-e7e8f33fb603c3bfa0479d7d924f2ad676a84317.zip | |
tcg: Fix tcg gen for vectorized absolute value
The fallback inline expansion for vectorized absolute value,
when the host doesn't support such an insn was flawed.
E.g. when a vector of bytes has all elements negative, mask
will be 0xffff_ffff_ffff_ffff. Subtracting mask only adds 1
to the low element instead of all elements becase -mask is 1
and not 0x0101_0101_0101_0101.
Signed-off-by: Stephen Long <steplong@quicinc.com>
Message-Id: <20200813161818.190-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | tcg/tcg-op-gvec.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 3707c0effb..793d4ba64c 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2264,12 +2264,13 @@ static void gen_absv_mask(TCGv_i64 d, TCGv_i64 b, unsigned vece) tcg_gen_muli_i64(t, t, (1 << nbit) - 1); /* - * Invert (via xor -1) and add one (via sub -1). + * Invert (via xor -1) and add one. * Because of the ordering the msb is cleared, * so we never have carry into the next element. */ tcg_gen_xor_i64(d, b, t); - tcg_gen_sub_i64(d, d, t); + tcg_gen_andi_i64(t, t, dup_const(vece, 1)); + tcg_gen_add_i64(d, d, t); tcg_temp_free_i64(t); } |