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| author | David Hildenbrand | 2019-04-10 21:37:24 +0200 |
|---|---|---|
| committer | David Hildenbrand | 2019-05-17 10:54:13 +0200 |
| commit | ea8d7840f559d585ca88d8e12cfe8b11959fef10 (patch) | |
| tree | f6eea3db91a0c0399c2fb38e9e6c23db2bba65a7 | |
| parent | s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL * (diff) | |
| download | qemu-ea8d7840f559d585ca88d8e12cfe8b11959fef10.tar.gz qemu-ea8d7840f559d585ca88d8e12cfe8b11959fef10.tar.xz qemu-ea8d7840f559d585ca88d8e12cfe8b11959fef10.zip | |
s390x/tcg: Implement VECTOR SUBTRACT
We can use tcg_gen_sub2_i64() to do 128-bit subtraction and otherwise
existing gvec helpers.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
| -rw-r--r-- | target/s390x/insn-data.def | 2 | ||||
| -rw-r--r-- | target/s390x/translate_vx.inc.c | 17 |
2 files changed, 19 insertions, 0 deletions
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index f3bf9edfca..58a61f41ef 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -1174,6 +1174,8 @@ F(0xe77c, VSRL, VRR_c, V, 0, 0, 0, 0, vsrl, 0, IF_VEC) /* VECTOR SHIFT RIGHT LOGICAL BY BYTE */ F(0xe77d, VSRLB, VRR_c, V, 0, 0, 0, 0, vsrl, 0, IF_VEC) +/* VECTOR SUBTRACT */ + F(0xe7f7, VS, VRR_c, V, 0, 0, 0, 0, vs, 0, IF_VEC) #ifndef CONFIG_USER_ONLY /* COMPARE AND SWAP AND PURGE */ diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c index 5dfbf1bcd4..5f53ae7ec5 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -2123,3 +2123,20 @@ static DisasJumpType op_vsrl(DisasContext *s, DisasOps *o) tcg_temp_free_i64(shift); return DISAS_NEXT; } + +static DisasJumpType op_vs(DisasContext *s, DisasOps *o) +{ + const uint8_t es = get_field(s->fields, m4); + + if (es > ES_128) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } else if (es == ES_128) { + gen_gvec128_3_i64(tcg_gen_sub2_i64, get_field(s->fields, v1), + get_field(s->fields, v2), get_field(s->fields, v3)); + return DISAS_NEXT; + } + gen_gvec_fn_3(sub, es, get_field(s->fields, v1), get_field(s->fields, v2), + get_field(s->fields, v3)); + return DISAS_NEXT; +} |