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| author | Philippe Mathieu-Daudé | 2021-01-10 22:46:43 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-01-14 17:13:54 +0100 |
| commit | eaca85763bcd94ddac3fa11f8cc20e974dc11102 (patch) | |
| tree | 2c96a603bd1fe894c5d6e0af9bb206b83742c3d8 | |
| parent | target/mips: Remove CPU_NANOMIPS32 definition (diff) | |
| download | qemu-eaca85763bcd94ddac3fa11f8cc20e974dc11102.tar.gz qemu-eaca85763bcd94ddac3fa11f8cc20e974dc11102.tar.xz qemu-eaca85763bcd94ddac3fa11f8cc20e974dc11102.zip | |
target/mips: Remove vendor specific CPU definitions
Vendor specific CPU definitions are not very useful. Use the
ISA definitions instead, which are more helpful when looking
at the various CPU definitions.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210112210152.2072996-4-f4bug@amsat.org>
| -rw-r--r-- | target/mips/cpu-defs.c.inc | 12 | ||||
| -rw-r--r-- | target/mips/mips-defs.h | 5 |
2 files changed, 7 insertions, 10 deletions
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 9f7bac8793..e03b2a998c 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -531,7 +531,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 40, .PABITS = 32, - .insn_flags = CPU_VR54XX, + .insn_flags = CPU_MIPS4 | INSN_VR54XX, .mmu_type = MMU_TYPE_R4000, }, { @@ -781,7 +781,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 40, .PABITS = 40, - .insn_flags = CPU_LOONGSON2E, + .insn_flags = CPU_MIPS3 | INSN_LOONGSON2E, .mmu_type = MMU_TYPE_R4000, }, { @@ -801,7 +801,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 40, .PABITS = 40, - .insn_flags = CPU_LOONGSON2F, + .insn_flags = CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI, .mmu_type = MMU_TYPE_R4000, }, { @@ -830,7 +830,8 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 42, .PABITS = 48, - .insn_flags = CPU_LOONGSON3A, + .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | + ASE_LMMI | ASE_LEXT, .mmu_type = MMU_TYPE_R4000, }, { @@ -887,7 +888,8 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 48, .PABITS = 48, - .insn_flags = CPU_LOONGSON3A, + .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | + ASE_LMMI | ASE_LEXT, .mmu_type = MMU_TYPE_R4000, }, { diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 3704db8553..0a12d982a7 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -60,9 +60,6 @@ #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) -#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) -#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) -#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) #define CPU_MIPS64 (ISA_MIPS3) @@ -86,8 +83,6 @@ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) -#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT) - /* * Strictly follow the architecture standard: * - Disallow "special" instruction handling for PMON/SPIM. |