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| author | Alistair Francis | 2020-01-21 06:36:57 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2020-03-17 01:03:13 +0100 |
| commit | ed5abf46b3c414ef58e647145f19b3966700b206 (patch) | |
| tree | 118e2d70b680eda5c99f5ecdc0c43414988b8f4c | |
| parent | Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200316-pull-request' ... (diff) | |
| download | qemu-ed5abf46b3c414ef58e647145f19b3966700b206.tar.gz qemu-ed5abf46b3c414ef58e647145f19b3966700b206.tar.xz qemu-ed5abf46b3c414ef58e647145f19b3966700b206.zip | |
target/riscv: Correctly implement TSR trap
As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't
correctly handling illegal instructions based on the value of MSTATUS_TSR
and the current privledge level.
This patch fixes the issue raised in the bug by raising an illegal
instruction if TSR is set and we are in S-Mode.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Jonathan Behrens <jonathan@fintelia.io
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
| -rw-r--r-- | target/riscv/op_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 8736f689c2..c6412f680c 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -85,7 +85,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) } if (env->priv_ver >= PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TSR)) { + get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } |