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| author | Shahab Vahedi | 2019-04-20 09:22:37 +0200 |
|---|---|---|
| committer | Richard Henderson | 2019-04-25 19:40:06 +0200 |
| commit | ef5dae6805cce7b59d129d801bdc5db71bcbd60d (patch) | |
| tree | 97b548ec3c78e5e1b12efbf534cc5610bae1b021 | |
| parent | tcg/arm: Restrict constant pool displacement to 12 bits (diff) | |
| download | qemu-ef5dae6805cce7b59d129d801bdc5db71bcbd60d.tar.gz qemu-ef5dae6805cce7b59d129d801bdc5db71bcbd60d.tar.xz qemu-ef5dae6805cce7b59d129d801bdc5db71bcbd60d.zip | |
cputlb: Fix io_readx() to respect the access_type
This change adapts io_readx() to its input access_type. Currently
io_readx() treats any memory access as a read, although it has an
input argument "MMUAccessType access_type". This results in:
1) Calling the tlb_fill() only with MMU_DATA_LOAD
2) Considering only entry->addr_read as the tlb_addr
Buglink: https://bugs.launchpad.net/qemu/+bug/1825359
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Shahab Vahedi <shahab.vahedi@gmail.com>
Message-Id: <20190420072236.12347-1-shahab.vahedi@gmail.com>
[rth: Remove assert; fix expression formatting.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | accel/tcg/cputlb.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 88cc8389e9..f2f618217d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -878,10 +878,11 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, CPUTLBEntry *entry; target_ulong tlb_addr; - tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); + tlb_fill(cpu, addr, size, access_type, mmu_idx, retaddr); entry = tlb_entry(env, mmu_idx, addr); - tlb_addr = entry->addr_read; + tlb_addr = (access_type == MMU_DATA_LOAD ? + entry->addr_read : entry->addr_code); if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { /* RAM access */ uintptr_t haddr = addr + entry->addend; |