summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorPeter Crosthwaite2014-04-01 06:31:09 +0200
committerPeter Maydell2014-04-17 22:34:06 +0200
commitf727d0e6219e6d5a9f91326f01b85aa563e37bb9 (patch)
tree94fa3b315fa7e8ab3f77d6a0cd6ce6103c95edbd
parenttarget-arm/gdbstub64.c: remove useless 'break' statement. (diff)
downloadqemu-f727d0e6219e6d5a9f91326f01b85aa563e37bb9.tar.gz
qemu-f727d0e6219e6d5a9f91326f01b85aa563e37bb9.tar.xz
qemu-f727d0e6219e6d5a9f91326f01b85aa563e37bb9.zip
timer: cadence_ttc: Fix match register write logic
This switch logic should not fall through. Fix. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 74147b4c017c904364955cc73107f90e6ac8ba74.1396326389.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/timer/cadence_ttc.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c
index a279bced78..28cb328f9b 100644
--- a/hw/timer/cadence_ttc.c
+++ b/hw/timer/cadence_ttc.c
@@ -346,11 +346,13 @@ static void cadence_ttc_write(void *opaque, hwaddr offset,
case 0x34:
case 0x38:
s->reg_match[0] = value & 0xffff;
+ break;
case 0x3c: /* match register */
case 0x40:
case 0x44:
s->reg_match[1] = value & 0xffff;
+ break;
case 0x48: /* match register */
case 0x4c: