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| author | Philippe Mathieu-Daudé | 2021-03-04 19:02:56 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-03-13 20:29:36 +0100 |
| commit | f8ead0d7bdebd81f4d8457c48f1d003fd4d94c69 (patch) | |
| tree | 60ad12571dc742a5c9518ebf19be853a7d57dea7 | |
| parent | hw/mips/gt64xxx: Rename trace events related to interrupt registers (diff) | |
| download | qemu-f8ead0d7bdebd81f4d8457c48f1d003fd4d94c69.tar.gz qemu-f8ead0d7bdebd81f4d8457c48f1d003fd4d94c69.tar.xz qemu-f8ead0d7bdebd81f4d8457c48f1d003fd4d94c69.zip | |
hw/mips/gt64xxx: Trace accesses to ISD registers
Trace all accesses to Internal Space Decode (ISD) registers.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-6-f4bug@amsat.org>
| -rw-r--r-- | hw/mips/gt64xxx_pci.c | 2 | ||||
| -rw-r--r-- | hw/mips/trace-events | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 9a12d00d1e..43349d6837 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -387,6 +387,7 @@ static void gt64120_writel(void *opaque, hwaddr addr, PCIHostState *phb = PCI_HOST_BRIDGE(s); uint32_t saddr = addr >> 2; + trace_gt64120_write(addr, val); if (!(s->regs[GT_CPU] & 0x00001000)) { val = bswap32(val); } @@ -966,6 +967,7 @@ static uint64_t gt64120_readl(void *opaque, if (!(s->regs[GT_CPU] & 0x00001000)) { val = bswap32(val); } + trace_gt64120_read(addr, val); return val; } diff --git a/hw/mips/trace-events b/hw/mips/trace-events index b7e934c393..13ee731a48 100644 --- a/hw/mips/trace-events +++ b/hw/mips/trace-events @@ -1,4 +1,6 @@ # gt64xxx_pci.c +gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64 +gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64 gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 |