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| author | Frank Chang | 2020-07-10 12:48:18 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-07-14 02:25:37 +0200 |
| commit | fbcbafa2c1c33ae6630e7717f7f4141befb5b31a (patch) | |
| tree | a91a4fa832380d21ccfae7bae7760e2769e32e94 | |
| parent | target/riscv: fix return value of do_opivx_widen() (diff) | |
| download | qemu-fbcbafa2c1c33ae6630e7717f7f4141befb5b31a.tar.gz qemu-fbcbafa2c1c33ae6630e7717f7f4141befb5b31a.tar.xz qemu-fbcbafa2c1c33ae6630e7717f7f4141befb5b31a.zip | |
target/riscv: fix vill bit index in vtype register
vill bit is at vtype[XLEN-1].
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-5-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eef20ca6e5..a804a5d0ba 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -98,7 +98,7 @@ FIELD(VTYPE, VLMUL, 0, 2) FIELD(VTYPE, VSEW, 2, 3) FIELD(VTYPE, VEDIV, 5, 2) FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) -FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1) +FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) struct CPURISCVState { target_ulong gpr[32]; |