diff options
| author | Bin Meng | 2020-10-28 06:30:06 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-11-03 16:17:23 +0100 |
| commit | 0f25065cb616f74729383fbf30369c374305ebb1 (patch) | |
| tree | bd068b95daa705a154638e7932bdebf16462639c /MAINTAINERS | |
| parent | hw/riscv: microchip_pfsoc: Connect the IOSCB module (diff) | |
| download | qemu-0f25065cb616f74729383fbf30369c374305ebb1.tar.gz qemu-0f25065cb616f74729383fbf30369c374305ebb1.tar.xz qemu-0f25065cb616f74729383fbf30369c374305ebb1.zip | |
hw/misc: Add Microchip PolarFire SoC SYSREG module support
This creates a minimum model for Microchip PolarFire SoC SYSREG
module. It only implements the ENVM_CR register to tell guest
software that eNVM is running at the configured divider rate.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-7-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 0e597c2989..dd16606bcd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1329,10 +1329,12 @@ F: hw/riscv/microchip_pfsoc.c F: hw/char/mchp_pfsoc_mmuart.c F: hw/misc/mchp_pfsoc_dmc.c F: hw/misc/mchp_pfsoc_ioscb.c +F: hw/misc/mchp_pfsoc_sysreg.c F: include/hw/riscv/microchip_pfsoc.h F: include/hw/char/mchp_pfsoc_mmuart.h F: include/hw/misc/mchp_pfsoc_dmc.h F: include/hw/misc/mchp_pfsoc_ioscb.h +F: include/hw/misc/mchp_pfsoc_sysreg.h RX Machines ----------- |