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| author | Peter Maydell | 2021-08-12 11:33:32 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-09-01 12:08:18 +0200 |
| commit | 2f9db77ea8330db9d038603055e0543512365283 (patch) | |
| tree | eb8850a1bcf7d1aca9a8f30e2a6a38ca305b4f5c /MAINTAINERS | |
| parent | tests/arm-cpu-features: Add A64FX processor related tests (diff) | |
| download | qemu-2f9db77ea8330db9d038603055e0543512365283.tar.gz qemu-2f9db77ea8330db9d038603055e0543512365283.tar.xz qemu-2f9db77ea8330db9d038603055e0543512365283.zip | |
arm: Move M-profile RAS register block into its own device
Currently we implement the RAS register block within the NVIC device.
It isn't really very tightly coupled with the NVIC proper, so instead
move it out into a sysbus device of its own and have the top level
ARMv7M container create it and map it into memory at the right
address.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Message-id: 20210812093356.1946-2-peter.maydell@linaro.org
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index dffcb651f4..f9d843ce0a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -617,6 +617,7 @@ F: hw/intc/gic_internal.h F: hw/misc/a9scu.c F: hw/misc/arm11scu.c F: hw/misc/arm_l2x0.c +F: hw/misc/armv7m_ras.c F: hw/timer/a9gtimer* F: hw/timer/arm* F: include/hw/arm/arm*.h @@ -626,6 +627,7 @@ F: include/hw/misc/arm11scu.h F: include/hw/timer/a9gtimer.h F: include/hw/timer/arm_mptimer.h F: include/hw/timer/armv7m_systick.h +F: include/hw/misc/armv7m_ras.h F: tests/qtest/test-arm-mptimer.c Exynos |