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| author | Bin Meng | 2020-10-28 06:30:02 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-11-03 16:17:23 +0100 |
| commit | 3400b15bbe0fbc672fee9a18268154b07a1fed2e (patch) | |
| tree | 8481d450f42487041164e70c0181c33983c0a1e7 /MAINTAINERS | |
| parent | hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps (diff) | |
| download | qemu-3400b15bbe0fbc672fee9a18268154b07a1fed2e.tar.gz qemu-3400b15bbe0fbc672fee9a18268154b07a1fed2e.tar.xz qemu-3400b15bbe0fbc672fee9a18268154b07a1fed2e.zip | |
hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support
The PolarFire SoC DDR Memory Controller mainly includes 2 modules,
called SGMII PHY module and the CFG module, as documented in the
chipset datasheet.
This creates a single file that groups these 2 modules, providing
the minimum functionalities that make the HSS DDR initialization
codes happy.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-3-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index c1d16026ba..d370158069 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1327,8 +1327,10 @@ L: qemu-riscv@nongnu.org S: Supported F: hw/riscv/microchip_pfsoc.c F: hw/char/mchp_pfsoc_mmuart.c +F: hw/misc/mchp_pfsoc_dmc.c F: include/hw/riscv/microchip_pfsoc.h F: include/hw/char/mchp_pfsoc_mmuart.h +F: include/hw/misc/mchp_pfsoc_dmc.h RX Machines ----------- |