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| author | Peter Maydell | 2018-06-22 14:28:39 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-06-22 14:28:39 +0200 |
| commit | 344f4b1581f3d629954a1623736677827a0af750 (patch) | |
| tree | 68704f1435c601484de269b672c6443e7407b7c6 /MAINTAINERS | |
| parent | xlnx-zynqmp: Swap Cortex-R5 for Cortex-R5F (diff) | |
| download | qemu-344f4b1581f3d629954a1623736677827a0af750.tar.gz qemu-344f4b1581f3d629954a1623736677827a0af750.tar.xz qemu-344f4b1581f3d629954a1623736677827a0af750.zip | |
hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller
Implement the Arm TrustZone Memory Protection Controller, which sits
in front of RAM and allows secure software to configure it to either
pass through or reject transactions.
We implement the MPC as a QEMU IOMMU, which will direct transactions
either through to the devices and memory behind it or to a special
"never works" AddressSpace if they are blocked.
This initial commit implements the skeleton of the device:
* it always permits accesses
* it doesn't implement most of the registers
* it doesn't implement the interrupt or other behaviour
for blocked transactions
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20180620132032.28865-2-peter.maydell@linaro.org
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index f222bf8b16..b8b4e60c06 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -457,6 +457,8 @@ F: hw/char/cmsdk-apb-uart.c F: include/hw/char/cmsdk-apb-uart.h F: hw/misc/tz-ppc.c F: include/hw/misc/tz-ppc.h +F: hw/misc/tz-mpc.c +F: include/hw/misc/tz-mpc.h ARM cores M: Peter Maydell <peter.maydell@linaro.org> |