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authorAlistair Francis2020-04-23 19:50:09 +0200
committerAlistair Francis2020-06-03 18:11:51 +0200
commit36b80ad99f7ea4979a4c5fc6e4072619b405e3b0 (patch)
tree9ba62390cd163c7be8fae917cedeabeadf3d0160 /MAINTAINERS
parenttarget/riscv: Don't set PMP feature in the cpu init (diff)
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target/riscv: Add the lowRISC Ibex CPU
Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture. For more details on lowRISC see here: https://github.com/lowRISC/ibex Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
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