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| author | Peter Maydell | 2021-02-19 15:45:53 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-03-08 18:20:02 +0100 |
| commit | 4239b311467bea86578d9da3cd22909de69d7af7 (patch) | |
| tree | 08cda6fa9220594cedb44f70909324b1bf09bf79 /MAINTAINERS | |
| parent | hw/arm/Kconfig: Move ARMSSE_CPUID and ARMSSE_MHU stanzas to hw/misc (diff) | |
| download | qemu-4239b311467bea86578d9da3cd22909de69d7af7.tar.gz qemu-4239b311467bea86578d9da3cd22909de69d7af7.tar.xz qemu-4239b311467bea86578d9da3cd22909de69d7af7.zip | |
hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block
The SSE-300 has a new register block CPU<N>_PWRCTRL. There is one
instance of this per CPU in the system (so just one for the SSE-300),
and as well as the usual CIDR/PIDR ID registers it has just one
register, CPUPWRCFG. This register allows the guest to configure
behaviour of the system in power-down and deep-sleep states. Since
QEMU does not model those, we make the register a dummy
reads-as-written implementation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-21-peter.maydell@linaro.org
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index ea206fc900..bd863cfeca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -747,6 +747,8 @@ F: hw/misc/iotkit-sysctl.c F: include/hw/misc/iotkit-sysctl.h F: hw/misc/iotkit-sysinfo.c F: include/hw/misc/iotkit-sysinfo.h +F: hw/misc/armsse-cpu-pwrctrl.c +F: include/hw/misc/armsse-cpu-pwrctrl.h F: hw/misc/armsse-cpuid.c F: include/hw/misc/armsse-cpuid.h F: hw/misc/armsse-mhu.c |