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| author | Peter Maydell | 2016-02-26 17:02:00 +0100 |
|---|---|---|
| committer | Peter Maydell | 2016-02-26 17:02:00 +0100 |
| commit | 6e378dd214fbbae8138ff011ec3de7ddf13a445f (patch) | |
| tree | 5ce6d8aca244eb11dd94daa2a6b94afdc038f124 /MAINTAINERS | |
| parent | Merge remote-tracking branch 'remotes/amit-migration/tags/migration-for-2.6-5... (diff) | |
| parent | target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF (diff) | |
| download | qemu-6e378dd214fbbae8138ff011ec3de7ddf13a445f.tar.gz qemu-6e378dd214fbbae8138ff011ec3de7ddf13a445f.tar.xz qemu-6e378dd214fbbae8138ff011ec3de7ddf13a445f.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160226' into staging
target-arm queue:
* Clean up handling of bad mode switches writing to CPSR, and implement
the ARMv8 requirement that they set PSTATE.IL
* Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps on perf monitor
register accesses
* Don't implement stellaris-pl061-only registers on generic-pl061
* Fix SD card handling for raspi
* Add missing include files to MAINTAINERS
* Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW
* Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF
# gpg: Signature made Fri 26 Feb 2016 15:19:07 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
* remotes/pmaydell/tags/pull-target-arm-20160226:
target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF
target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW
sdhci: add quirk property for card insert interrupt status on Raspberry Pi
sdhci: Revert "add optional quirk property to disable card insertion/removal interrupts"
MAINTAINERS: Add some missing ARM related header files
raspi: fix SD card with recent sdhci changes
ARM: PL061: Checking register r/w accesses to reserved area
target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps
target-arm: Fix handling of SDCR for 32-bit code
target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1
target-arm: Make mode switches from Hyp via CPS and MRS illegal
target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL
target-arm: Forbid mode switch to Mon from Secure EL1
target-arm: Add Hyp mode checks to bad_mode_switch()
target-arm: Add comment about not implementing NSACR.RFR
target-arm: In cpsr_write() ignore mode switches from User mode
linux-user: Use restrictive mask when calling cpsr_write()
target-arm: Raw CPSR writes should skip checks and bank switching
target-arm: Add write_type argument to cpsr_write()
target-arm: Give CPSR setting on 32-bit exception return its own helper
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 5fafa815ad..caa5260e7c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -363,6 +363,7 @@ M: Dmitry Solodkiy <d.solodkiy@samsung.com> L: qemu-arm@nongnu.org S: Maintained F: hw/*/exynos* +F: include/hw/arm/exynos4210.h Calxeda Highbank M: Rob Herring <robh@kernel.org> @@ -390,6 +391,7 @@ L: qemu-arm@nongnu.org S: Odd fixes F: hw/*/imx* F: hw/arm/kzm.c +F: include/hw/arm/fsl-imx31.h Integrator CP M: Peter Maydell <peter.maydell@linaro.org> @@ -432,6 +434,7 @@ F: hw/arm/spitz.c F: hw/arm/tosa.c F: hw/arm/z2.c F: hw/*/pxa2xx* +F: include/hw/arm/pxa.h Stellaris M: Peter Maydell <peter.maydell@linaro.org> @@ -768,6 +771,7 @@ OMAP M: Peter Maydell <peter.maydell@linaro.org> S: Maintained F: hw/*/omap* +F: include/hw/arm/omap.h IPack M: Alberto Garcia <berto@igalia.com> |