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authorVijai Kumar K2021-04-01 20:14:55 +0200
committerAlistair Francis2021-05-11 12:01:38 +0200
commit7a261bafc8ee01294cc709366810798bec4fe2f7 (patch)
treefd3972669ac0f98688b131b3e6c18ac9f11e34a7 /MAINTAINERS
parenttarget/riscv: Add Shakti C class CPU (diff)
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riscv: Add initial support for Shakti C machine
Add support for emulating Shakti reference platform based on C-class running on arty-100T board. https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst Signed-off-by: Vijai Kumar K <vijai@behindbytes.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210401181457.73039-3-vijai@behindbytes.com [Changes by AF: - Check for mstate->firmware before loading it ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'MAINTAINERS')
-rw-r--r--MAINTAINERS7
1 files changed, 7 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 06642d9799..bfa5adcb1a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1415,6 +1415,13 @@ F: include/hw/misc/mchp_pfsoc_dmc.h
F: include/hw/misc/mchp_pfsoc_ioscb.h
F: include/hw/misc/mchp_pfsoc_sysreg.h
+Shakti C class SoC
+M: Vijai Kumar K <vijai@behindbytes.com>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: hw/riscv/shakti_c.c
+F: include/hw/riscv/shakti_c.h
+
SiFive Machines
M: Alistair Francis <Alistair.Francis@wdc.com>
M: Bin Meng <bin.meng@windriver.com>