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| author | Bin Meng | 2020-10-28 06:30:04 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-11-03 16:17:23 +0100 |
| commit | a937b302831f12094437cdbdfc859bff9f093525 (patch) | |
| tree | 1e261b3c39df4066f0da2f61ffb2da9cee3df64c /MAINTAINERS | |
| parent | hw/riscv: microchip_pfsoc: Connect DDR memory controller modules (diff) | |
| download | qemu-a937b302831f12094437cdbdfc859bff9f093525.tar.gz qemu-a937b302831f12094437cdbdfc859bff9f093525.tar.xz qemu-a937b302831f12094437cdbdfc859bff9f093525.zip | |
hw/misc: Add Microchip PolarFire SoC IOSCB module support
This creates a model for PolarFire SoC IOSCB [1] module. It actually
contains lots of sub-modules like various PLLs to control different
peripherals. Only the mininum capabilities are emulated to make the
HSS DDR memory initialization codes happy. Lots of sub-modules are
created as an unimplemented devices.
[1] PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm in
https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-5-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index d370158069..0e597c2989 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1328,9 +1328,11 @@ S: Supported F: hw/riscv/microchip_pfsoc.c F: hw/char/mchp_pfsoc_mmuart.c F: hw/misc/mchp_pfsoc_dmc.c +F: hw/misc/mchp_pfsoc_ioscb.c F: include/hw/riscv/microchip_pfsoc.h F: include/hw/char/mchp_pfsoc_mmuart.h F: include/hw/misc/mchp_pfsoc_dmc.h +F: include/hw/misc/mchp_pfsoc_ioscb.h RX Machines ----------- |