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| author | Alistair Francis | 2021-04-07 00:48:25 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-05-11 12:02:06 +0200 |
| commit | ab2c91286c0fca38e10af0908573e776c395445d (patch) | |
| tree | cee4169b241d462849d15052e17d1431bd0a025e /MAINTAINERS | |
| parent | target/riscv: Use RISCVException enum for CSR access (diff) | |
| download | qemu-ab2c91286c0fca38e10af0908573e776c395445d.tar.gz qemu-ab2c91286c0fca38e10af0908573e776c395445d.tar.xz qemu-ab2c91286c0fca38e10af0908573e776c395445d.zip | |
MAINTAINERS: Update the RISC-V CPU Maintainers
Update the RISC-V maintainers by removing Sagar and Bastian who haven't
been involved recently.
Also add Bin who has been helping with reviews.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 6564ba829c40ad9aa7d28f43be69d8eb5cf4b56b.1617749142.git.alistair.francis@wdc.com
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 7aaa304b1e..3ace764d29 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -295,9 +295,8 @@ F: tests/acceptance/machine_ppc.py RISC-V TCG CPUs M: Palmer Dabbelt <palmer@dabbelt.com> -M: Alistair Francis <Alistair.Francis@wdc.com> -M: Sagar Karandikar <sagark@eecs.berkeley.edu> -M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> +M: Alistair Francis <alistair.francis@wdc.com> +M: Bin Meng <bin.meng@windriver.com> L: qemu-riscv@nongnu.org S: Supported F: target/riscv/ |