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| author | Alistair Francis | 2021-06-18 09:27:54 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-06-24 14:00:12 +0200 |
| commit | df41cbd6bfa55dc3e69834f4402dbf776062c26e (patch) | |
| tree | 5f8c06787125e59d9c3dabb1a59dc3dd7c6853fa /MAINTAINERS | |
| parent | hw/char/ibex_uart: Make the register layout private (diff) | |
| download | qemu-df41cbd6bfa55dc3e69834f4402dbf776062c26e.tar.gz qemu-df41cbd6bfa55dc3e69834f4402dbf776062c26e.tar.xz qemu-df41cbd6bfa55dc3e69834f4402dbf776062c26e.zip | |
hw/timer: Initial commit of Ibex Timer
Add support for the Ibex timer. This is used with the RISC-V
mtime/mtimecmp similar to the SiFive CLINT.
We currently don't support changing the prescale or the timervalue.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 716fdea2244515ce86a2c46fe69467d013c03147.1624001156.git.alistair.francis@wdc.com
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 1a041eaf86..77e4570ea0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1364,11 +1364,9 @@ M: Alistair Francis <Alistair.Francis@wdc.com> L: qemu-riscv@nongnu.org S: Supported F: hw/riscv/opentitan.c -F: hw/char/ibex_uart.c -F: hw/intc/ibex_plic.c +F: hw/*/ibex_*.c F: include/hw/riscv/opentitan.h -F: include/hw/char/ibex_uart.h -F: include/hw/intc/ibex_plic.h +F: include/hw/*/ibex_*.h Microchip PolarFire SoC Icicle Kit M: Bin Meng <bin.meng@windriver.com> |