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| author | Havard Skinnemoen | 2020-09-11 07:20:48 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-09-14 15:24:15 +0200 |
| commit | e5a7ba8788056d0fb10b9ff587677ba78ca41ce9 (patch) | |
| tree | bceb72d73b8fe2eafbfbb7600e998d9f4f3023e2 /MAINTAINERS | |
| parent | hw/arm: versal-virt: Correct the tx/rx GEM clocks (diff) | |
| download | qemu-e5a7ba8788056d0fb10b9ff587677ba78ca41ce9.tar.gz qemu-e5a7ba8788056d0fb10b9ff587677ba78ca41ce9.tar.xz qemu-e5a7ba8788056d0fb10b9ff587677ba78ca41ce9.zip | |
hw/misc: Add NPCM7xx System Global Control Registers device model
Implement a device model for the System Global Control Registers in the
NPCM730 and NPCM750 BMC SoCs.
This is primarily used to enable SMP boot (the boot ROM spins reading
the SCRPAD register) and DDR memory initialization; other registers are
best effort for now.
The reset values of the MDLR and PWRON registers are determined by the
SoC variant (730 vs 750) and board straps respectively.
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-2-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index d817ee6c6f..c95a00c12d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -750,6 +750,14 @@ S: Odd Fixes F: hw/arm/musicpal.c F: docs/system/arm/musicpal.rst +Nuvoton NPCM7xx +M: Havard Skinnemoen <hskinnemoen@google.com> +M: Tyrone Ting <kfting@nuvoton.com> +L: qemu-arm@nongnu.org +S: Supported +F: hw/*/npcm7xx* +F: include/hw/*/npcm7xx* + nSeries M: Andrzej Zaborowski <balrogg@gmail.com> M: Peter Maydell <peter.maydell@linaro.org> |