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| author | Julia Suvorova | 2018-08-14 18:17:19 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-08-14 18:17:19 +0200 |
| commit | c4379b4874f4c522f6818f1720f295205d7cf34d (patch) | |
| tree | dcd5e13c26673e0a97d93aefdf75e5ca0c0d4ff1 /accel/tcg/cpu-exec.c | |
| parent | arm: Add ARMv6-M programmer's model support (diff) | |
| download | qemu-c4379b4874f4c522f6818f1720f295205d7cf34d.tar.gz qemu-c4379b4874f4c522f6818f1720f295205d7cf34d.tar.xz qemu-c4379b4874f4c522f6818f1720f295205d7cf34d.zip | |
nvic: Change NVIC to support ARMv6-M
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
Signed-off-by: Julia Suvorova <jusual@mail.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'accel/tcg/cpu-exec.c')
0 files changed, 0 insertions, 0 deletions