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| author | Richard Henderson | 2022-06-08 20:38:59 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-06-08 20:38:59 +0200 |
| commit | 414c54d515dba16bfaef643a8acec200c05f229a (patch) | |
| tree | 7e67548bc1de794e33dbee7ae802b23f3f953b5c /accel/tcg/user-exec.c | |
| parent | target/arm: Add isar_feature_aa64_sme (diff) | |
| download | qemu-414c54d515dba16bfaef643a8acec200c05f229a.tar.gz qemu-414c54d515dba16bfaef643a8acec200c05f229a.tar.xz qemu-414c54d515dba16bfaef643a8acec200c05f229a.zip | |
target/arm: Add ID_AA64SMFR0_EL1
This register is allocated from the existing block of id registers,
so it is already RES0 for cpus that do not implement SME.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'accel/tcg/user-exec.c')
0 files changed, 0 insertions, 0 deletions