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| author | Richard Henderson | 2021-02-13 14:03:13 +0100 |
|---|---|---|
| committer | Alex Bennée | 2021-02-18 09:19:12 +0100 |
| commit | d9bcb58a128344b87a26d6073caa2c6117ec211d (patch) | |
| tree | dacbb34633f794b80ffed58a13b0731c611af4a9 /accel/tcg | |
| parent | exec: Move TranslationBlock typedef to qemu/typedefs.h (diff) | |
| download | qemu-d9bcb58a128344b87a26d6073caa2c6117ec211d.tar.gz qemu-d9bcb58a128344b87a26d6073caa2c6117ec211d.tar.xz qemu-d9bcb58a128344b87a26d6073caa2c6117ec211d.zip | |
accel/tcg: Create io_recompile_replay_branch hook
Create a hook in which to split out the mips and
sh4 ifdefs from cpu_io_recompile.
[AJB: s/stoped/stopped/]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210208233906.479571-3-richard.henderson@linaro.org>
Message-Id: <20210213130325.14781-12-alex.bennee@linaro.org>
Diffstat (limited to 'accel/tcg')
| -rw-r--r-- | accel/tcg/translate-all.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 2c34adccce..99ca6f36b9 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -60,6 +60,7 @@ #include "sysemu/cpu-timers.h" #include "sysemu/tcg.h" #include "qapi/error.h" +#include "hw/core/tcg-cpu-ops.h" #include "internal.h" /* #define DEBUG_TB_INVALIDATE */ @@ -2421,6 +2422,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) CPUArchState *env = cpu->env_ptr; #endif TranslationBlock *tb; + CPUClass *cc; uint32_t n; tb = tcg_tb_lookup(retaddr); @@ -2430,11 +2432,18 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) } cpu_restore_state_from_tb(cpu, tb, retaddr, true); - /* On MIPS and SH, delay slot instructions can only be restarted if - they were already the first instruction in the TB. If this is not - the first instruction in a TB then re-execute the preceding - branch. */ + /* + * Some guests must re-execute the branch when re-executing a delay + * slot instruction. When this is the case, adjust icount and N + * to account for the re-execution of the branch. + */ n = 1; + cc = CPU_GET_CLASS(cpu); + if (cc->tcg_ops->io_recompile_replay_branch && + cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) { + cpu_neg(cpu)->icount_decr.u16.low++; + n = 2; + } #if defined(TARGET_MIPS) if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && env->active_tc.PC != tb->pc) { |