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| author | Peter Maydell | 2020-07-27 17:45:50 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-08-03 18:56:11 +0200 |
| commit | 13557fd392890cbd985bceba7f717e01efd674b8 (patch) | |
| tree | c4d5d792312b99073390774f2a4dd7e6def1e1f7 /accel | |
| parent | hw/arm/nrf51_soc: Set system_clock_scale (diff) | |
| download | qemu-13557fd392890cbd985bceba7f717e01efd674b8.tar.gz qemu-13557fd392890cbd985bceba7f717e01efd674b8.tar.xz qemu-13557fd392890cbd985bceba7f717e01efd674b8.zip | |
hw/timer/imx_epit: Avoid assertion when CR.SWR is written
The imx_epit device has a software-controllable reset triggered by
setting the SWR bit in the CR register. An error in commit cc2722ec83ad9
means that we will end up assert()ing if the guest does this, because
the code in imx_epit_write() starts ptimer transactions, and then
imx_epit_reset() also starts ptimer transactions, triggering
"ptimer_transaction_begin: Assertion `!s->in_transaction' failed".
The cleanest way to avoid this double-transaction is to move the
start-transaction for the CR write handling down below the check of
the SWR bit.
Fixes: https://bugs.launchpad.net/qemu/+bug/1880424
Fixes: cc2722ec83ad944505fe
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200727154550.3409-1-peter.maydell@linaro.org
Diffstat (limited to 'accel')
0 files changed, 0 insertions, 0 deletions