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| author | Richard Henderson | 2022-04-01 15:47:32 +0200 |
|---|---|---|
| committer | Richard Henderson | 2022-04-20 21:12:47 +0200 |
| commit | 5b6af141dac7a6a749030c9de33382374671b2ad (patch) | |
| tree | 95d333f0acb32ded6d8cb712e2901ead21a2ece5 /accel | |
| parent | tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCH (diff) | |
| download | qemu-5b6af141dac7a6a749030c9de33382374671b2ad.tar.gz qemu-5b6af141dac7a6a749030c9de33382374671b2ad.tar.xz qemu-5b6af141dac7a6a749030c9de33382374671b2ad.zip | |
accel/tcg: Remove ATOMIC_MMU_IDX
The last use of this macro was removed in f3e182b10013
("accel/tcg: Push trace info building into atomic_common.c.inc")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'accel')
| -rw-r--r-- | accel/tcg/cputlb.c | 1 | ||||
| -rw-r--r-- | accel/tcg/user-exec.c | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 2035b2ac0a..dd45e0467b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2552,7 +2552,6 @@ void cpu_stq_le_mmu(CPUArchState *env, target_ulong addr, uint64_t val, glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu) #define ATOMIC_MMU_CLEANUP -#define ATOMIC_MMU_IDX get_mmuidx(oi) #include "atomic_common.c.inc" diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 8edf0bbaa1..ac57324d4f 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -506,7 +506,6 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, #define ATOMIC_NAME(X) \ glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu) #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0) -#define ATOMIC_MMU_IDX MMU_USER_IDX #define DATA_SIZE 1 #include "atomic_template.h" |