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| author | Michael Clark | 2019-01-15 00:58:23 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-02-12 00:56:21 +0100 |
| commit | fb73883964099011d34c052658e5ad8be049da61 (patch) | |
| tree | 86f282b08a834767090233fdd02cc245b70e4561 /block/qcow2-refcount.c | |
| parent | RISC-V: Implement mstatus.TSR/TW/TVM (diff) | |
| download | qemu-fb73883964099011d34c052658e5ad8be049da61.tar.gz qemu-fb73883964099011d34c052658e5ad8be049da61.tar.xz qemu-fb73883964099011d34c052658e5ad8be049da61.zip | |
RISC-V: Use riscv prefix consistently on cpu helpers
* Add riscv prefix to raise_exception function
* Add riscv prefix to CSR read/write functions
* Add riscv prefix to signal handler function
* Add riscv prefix to get fflags function
* Remove redundant declaration of riscv_cpu_init
and rename cpu_riscv_init to riscv_cpu_init
* rename riscv_set_mode to riscv_cpu_set_mode
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'block/qcow2-refcount.c')
0 files changed, 0 insertions, 0 deletions