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| author | Peter Maydell | 2014-12-22 14:15:52 +0100 |
|---|---|---|
| committer | Peter Maydell | 2014-12-22 14:15:52 +0100 |
| commit | 7db96d6cf877d4bb8132462ec7dd19055ff968eb (patch) | |
| tree | 0321904ded033d9d754d4b3c2c45d05ad924ed77 /bootdevice.c | |
| parent | Merge remote-tracking branch 'remotes/kraxel/tags/pull-sdl-20141219-1' into s... (diff) | |
| parent | target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as firs... (diff) | |
| download | qemu-7db96d6cf877d4bb8132462ec7dd19055ff968eb.tar.gz qemu-7db96d6cf877d4bb8132462ec7dd19055ff968eb.tar.xz qemu-7db96d6cf877d4bb8132462ec7dd19055ff968eb.zip | |
Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20141221' into staging
TriCore RR, RR1 insn added and several bug fixes
# gpg: Signature made Sun 21 Dec 2014 18:39:11 GMT using RSA key ID 6B69CA14
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>"
* remotes/bkoppelmann/tags/pull-tricore-20141221:
target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode
target-tricore: Fix MFCR/MTCR insn and B format offset.
target-tricore: Add missing 1.6 insn of BOL opcode format
target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode
target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode
target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode
target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode
target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32
target-tricore: Fix mask handling JNZ.T being 7 bit long
target-tricore: pretty-print register dump and show more status registers
target-tricore: add missing 64-bit MOV in RLC format
target-tricore: typo in BOL format
target-tricore: fix offset masking in BOL format
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'bootdevice.c')
0 files changed, 0 insertions, 0 deletions