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| author | Richard Henderson | 2017-08-17 23:47:43 +0200 |
|---|---|---|
| committer | Richard Henderson | 2018-02-08 16:54:08 +0100 |
| commit | 770c2fc7bb70804ae9869995fd02dadd6d7656ac (patch) | |
| tree | eebf85125304f66591faaf92ec7d9b8381fbac3f /chardev/char-mux.c | |
| parent | target/arm: Use vector infrastructure for aa64 orr/bic immediate (diff) | |
| download | qemu-770c2fc7bb70804ae9869995fd02dadd6d7656ac.tar.gz qemu-770c2fc7bb70804ae9869995fd02dadd6d7656ac.tar.xz qemu-770c2fc7bb70804ae9869995fd02dadd6d7656ac.zip | |
tcg/i386: Add vector operations
The x86 vector instruction set is extremely irregular. With newer
editions, Intel has filled in some of the blanks. However, we don't
get many 64-bit operations until SSE4.2, introduced in 2009.
The subsequent edition was for AVX1, introduced in 2011, which added
three-operand addressing, and adjusts how all instructions should be
encoded.
Given the relatively narrow 2 year window between possible to support
and desirable to support, and to vastly simplify code maintainence,
I am only planning to support AVX1 and later cpus.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'chardev/char-mux.c')
0 files changed, 0 insertions, 0 deletions