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| author | Blue Swirl | 2011-10-27 22:27:07 +0200 |
|---|---|---|
| committer | Blue Swirl | 2011-10-27 22:27:07 +0200 |
| commit | b5a12aa204f842c8010ac9d2e4b115114dbf09f0 (patch) | |
| tree | b68aaa746a014fe70428204fdc682c11c83c7833 /configure | |
| parent | Merge branch 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydel... (diff) | |
| parent | target-sparc: Implement FALIGNDATA inline. (diff) | |
| download | qemu-b5a12aa204f842c8010ac9d2e4b115114dbf09f0.tar.gz qemu-b5a12aa204f842c8010ac9d2e4b115114dbf09f0.tar.xz qemu-b5a12aa204f842c8010ac9d2e4b115114dbf09f0.zip | |
Merge branch 'rth/vis2' of git://repo.or.cz/qemu/rth
* 'rth/vis2' of git://repo.or.cz/qemu/rth:
target-sparc: Implement FALIGNDATA inline.
target-sparc: Implement BMASK/BSHUFFLE.
target-sparc: Implement ALIGNADDR* inline.
target-sparc: Implement EDGE* instructions.
target-sparc: Implement fpack{16,32,fix}.
target-sparc: Implement PDIST.
target-sparc: Do exceptions management fully inside the helpers.
target-sparc: Change fpr representation to doubles.
target-sparc: Undo cpu_fpr rename.
target-sparc: Extract float128 move to a function.
target-sparc: Extract common code for floating-point operations.
target-sparc: Make FPU/VIS helpers const when possible.
target-sparc: Pass float64 parameters instead of dt0/1 temporaries.
target-sparc: Add accessors for double-precision fpr access.
target-sparc: Mark fprs dirty in store accessor.
target-sparc: Add accessors for single-precision fpr access.
Diffstat (limited to 'configure')
0 files changed, 0 insertions, 0 deletions