summaryrefslogtreecommitdiffstats
path: root/configure
diff options
context:
space:
mode:
authorRichard Henderson2021-09-17 20:08:09 +0200
committerRichard Henderson2021-10-30 18:52:04 +0200
commitba0e73336200a04f797ae0c13922146a135cb118 (patch)
tree09a3dd7150c4746ba5af15dc173e627d81de4d90 /configure
parentaccel/tcg: Fold cpu_exit_tb_from_sighandler into caller (diff)
downloadqemu-ba0e73336200a04f797ae0c13922146a135cb118.tar.gz
qemu-ba0e73336200a04f797ae0c13922146a135cb118.tar.xz
qemu-ba0e73336200a04f797ae0c13922146a135cb118.zip
configure: Merge riscv32 and riscv64 host architectures
The existing code for safe-syscall.inc.S will compile without change for riscv32 and riscv64. We may also drop the meson.build stanza that merges them for tcg/. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'configure')
-rwxr-xr-xconfigure8
1 files changed, 2 insertions, 6 deletions
diff --git a/configure b/configure
index 039467c04b..d57ad58342 100755
--- a/configure
+++ b/configure
@@ -570,11 +570,7 @@ elif check_define __s390__ ; then
cpu="s390"
fi
elif check_define __riscv ; then
- if check_define _LP64 ; then
- cpu="riscv64"
- else
- cpu="riscv32"
- fi
+ cpu="riscv"
elif check_define __arm__ ; then
cpu="arm"
elif check_define __aarch64__ ; then
@@ -587,7 +583,7 @@ ARCH=
# Normalise host CPU name and set ARCH.
# Note that this case should only have supported host CPUs, not guests.
case "$cpu" in
- ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64)
+ ppc|ppc64|s390x|sparc64|x32|riscv)
;;
ppc64le)
ARCH="ppc64"