Merge remote branch 'rth/axp-next' into alpha-merge

* rth/axp-next: (26 commits)
  target-alpha: Implement TLB flush primitives.
  target-alpha: Use a fixed frequency for the RPCC in system mode.
  target-alpha: Trap for unassigned and unaligned addresses.
  target-alpha: Remap PIO space for 43-bit KSEG for EV6.
  target-alpha: Implement cpu_alpha_handle_mmu_fault for system mode.
  target-alpha: Implement more CALL_PAL values inline.
  target-alpha: Disable interrupts properly.
  target-alpha: All ISA checks to use TB->FLAGS.
  target-alpha: Swap shadow registers moving to/from PALmode.
  target-alpha: Implement do_interrupt for system mode.
  target-alpha: Add IPRs to be used by the emulation PALcode.
  target-alpha: Use kernel mmu_idx for pal_mode.
  target-alpha: Add various symbolic constants.
  target-alpha: Use do_restore_state for arithmetic exceptions.
  target-alpha: Tidy up arithmetic exceptions.
  target-alpha: Tidy exception constants.
  target-alpha: Enable the alpha-softmmu target.
  target-alpha: Rationalize internal processor registers.
  target-alpha: Merge HW_REI and HW_RET implementations.
  target-alpha: Cleanup MMU modes.
  ...

1 files changed, 30 insertions, 3 deletions

diff --git a/cpu-exec.c b/cpu-exec.c
index 6ddd8dd1ae..e1de56b397 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -488,9 +488,36 @@ int cpu_exec(CPUState *env1)
                         next_tb = 0;
                     }
 #elif defined(TARGET_ALPHA)
-                    if (interrupt_request & CPU_INTERRUPT_HARD) {
-                        do_interrupt(env);
-                        next_tb = 0;
+                    {
+                        int idx = -1;
+                        /* ??? This hard-codes the OSF/1 interrupt levels.  */
+		        switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
+                        case 0 ... 3:
+                            if (interrupt_request & CPU_INTERRUPT_HARD) {
+                                idx = EXCP_DEV_INTERRUPT;
+                            }
+                            /* FALLTHRU */
+                        case 4:
+                            if (interrupt_request & CPU_INTERRUPT_TIMER) {
+                                idx = EXCP_CLK_INTERRUPT;
+                            }
+                            /* FALLTHRU */
+                        case 5:
+                            if (interrupt_request & CPU_INTERRUPT_SMP) {
+                                idx = EXCP_SMP_INTERRUPT;
+                            }
+                            /* FALLTHRU */
+                        case 6:
+                            if (interrupt_request & CPU_INTERRUPT_MCHK) {
+                                idx = EXCP_MCHK;
+                            }
+                        }
+                        if (idx >= 0) {
+                            env->exception_index = idx;
+                            env->error_code = 0;
+                            do_interrupt(env);
+                            next_tb = 0;
+                        }
                     }
 #elif defined(TARGET_CRIS)
                     if (interrupt_request & CPU_INTERRUPT_HARD